This application claims priority under 35 U.S.C. xc2xa7xc2xa7119 and/or 365 to 99688.0 filed in Great Britain on Jul. 16, 1999; the entire content of which is hereby incorporated by reference.
This invention relates to integrated circuits, and in particular to integrated analog filter circuits.
In integrated circuits, it is extremely difficult to realise inductors, except with very low inductances. As a result, it is generally only possible to use RC filters (with resistors and capacitors), except at very high frequencies.
As an alternative, active filters are often used. Such devices use transconductance elements such as transistors, in combination with capacitors, which together can form integrators or gyrators, and can emulate the impedance of inductors.
An integrated gyrator structure, for use in a very high frequency filter, is proposed in Nauta xe2x80x9cA CMOS Transconductance-C Filter Technique for Very High Frequenciesxe2x80x9d, IEEE Journal of Solid State Circuits, Vol. 27, No. 2, February 1992. The author""s first order analysis of the circuit concluded that the proposed gyrator behaves stably.
The author also proposed a Q-tuning loop, to provide a controllable Q-value for the filter at very high frequencies.
The present invention proceeds from the realization that this first order analysis of the prior art structure results in an incomplete understanding of the structure.
In particular, a more detailed analysis of the MOS transistors reveals that each MOS transistor adds a delay element due to the actions of charged particles in the channel of the transistor. More specifically, the nonquasi-static behaviour of the channel charge adds a delay, which could be approximated as a parasitic pole, in the frequency characteristic of the transconductance of the device. The channel delays of the transistors can make the gyrator unstable, in particular in the case of higher order filters (which are often required, in order to provide the necessary filter characteristics), or at higher frequencies (when the channel delay becomes more of a problem).
Moreover, the channel delay means that the prior art Q-tuning loop does not function as intended.
The present invention attempts to overcome the disadvantages of the prior art, by taking the channel delay of the transistors into consideration.
Specifically, the invention relates in one aspect to the design of an integrated circuit device, in a way which includes consideration of the channel delay of the transistors.
In another aspect, the invention relates to an integrated circuit device, in which the channel delay of a transistor is compensated by means of series feedback.
In another aspect, the invention relates to the design method, which accounts for the channel delay.